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SY58621L
Precision 3.2Gbps CML/LVPECL Backplane Transceiver with Integrated Loopback
General Description
The SY58621L is a low jitter, high-speed transceiver with a variable swing LVPECL transmitter buffer and a CML high-gain receiver optimized for precision telecom and enterprise server transmission line and backplane data management. The SY58621L distributes data to 3.2Gbps guaranteed over temperature and voltage. The SY58621L transmitter differential input includes Micrel's unique, patented 3-pin input termination architecture that directly interfaces to any (AC- or DCcoupled) differential signal as small as 100mV (200mVPP) without any termination resistor network in the signal path. The receiver differential input is optimized to interface directly to AC-coupled signals as small as 10mV (20mVPP). The receiver output is 50 source-terminated CML and the transmitter output is variable swing 80mV to 800mV LVPECL with extremely fast rise/fall time. To support remote self-testing, the SY58621L features a high-speed loopback test mode. The input control signal LOOPBACK enables an internal loopback path from the transmitter input to the receiver output. The SY58621L operates from a 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY58621L is part of Micrel's high-speed, Precision Edge(R) product line. For applications that requires a CML receiver and transmitter, consider the SY58620L. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge(R)
Features
* Guaranteed AC performance over temperature and voltage: - Maximum Throughput 3.2Gbps - <160ps tr/tf time * Transmitter - Patented input termination directly interfaces to ACor DC-coupled differential inputs - Variable swing LVPECL output * Receiver - 32dB high-gain Input - Internal 50 input termination - Accepts AC-coupled input signals as small as 10mV (20mvPP) - 400mV (800mVPP) differential CML output swing * Loss-of-Signal (LOS) - High-gain, TTL-compatible LOS output with internal 4.75k pull-up - Programmable LOS level set * Ultra-low jitter design - <5psRMS random jitter * Patent-pending MUX isolates the receiver and the transmitter channels minimizing on crosstalk * Selectable loopback diagnostic mode * Output enables on transmitter and receiver outputs * Power supply +3.3V 10% * Industrial temperature range -40C to +85C * Available in 24-pin (4mm x 4mm) MLFTM
Applications
* * * * Backplane management Active cable transceivers SONET/SDH data/clock applications 4X Fibre Channel applications
Markets
* * * * Precision telecom Enterprise server ATE Test and measurement
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are trademarks of Amkor Technology, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
September 2005
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SY58621L
Typical Applications
Functional Block Diagram
Note: It is recommended that RLOSLVL 10k. See the "Typical Operating Characteristics" section for more details.
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SY58621L
Ordering Information(1)
Part Number SY58621LMG SY58621LMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-24 MLF-24
Operating Range Industrial Industrial
Package Marking 621L with Pb-Free bar-line indicator 621L with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
24-Pin MLFTM (MLF-24)
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SY58621L
Pin Description
Inputs
Pin Number 23 Pin Name LOOPBACK Pin Description LOOPBACK Mode Control. TTL/CMOS control input. LOOPBACK is an active HIGH signal used to control the LOOPBACK MUX. LOOPBACK is internally connected to a 25k pulldown resistor and will default to a LOW state if left open. VTH = VCC/2. Receiver Output Control. TTL/CMOS control input. /RXEN is an active LOW signal used to enable the receiver outputs. /RXEN is internally connected to a 25k pull-down resistor and will default to a LOW state if left open. VTH = VCC/2. Receiver Differential Input. Input accepts AC differential signals as small as 10mV (20mVPP). Each pin internally terminates to VCC_RXIN-1.3V (internal voltage reference) through 50. Input will default to an indeterminate state if left open. See figure 6b. Transmitter Output Control. TTL/CMOS control input. /TXEN is an active LOW signal used to enable the transmitter output. /TXEN is internally connected to a 25k pull-down resistor and will default to a LOW state if left open. VTH = VCC/2. Transmitter Differential Input. Input accepts AC- or DC-coupled differential signals as small as 100mV (200mVPP). Each pin terminates to the TXVT pin through 50. Note that this input will default to an indeterminate state if left open. See figure 6a. Transmitter Output Swing Control. Input that controls the output amplitude of the transmitter. The operating range of the control input is from VREF_CTRL (max swing) to VCC (min swing). Control of the output swing can be obtained by using a variable resistor between VREF_CTRL and VCC_TXQ through a wiper driving TXVCTRL. Setting TXVCTRL to VCC_TXQ sets the output swing to min swing. Refer to the "Interface Applications" and "Output Stage" sections for more details. Input Termination Center-Tap. Each side of the transmitter differential input pair terminates to the TXVT pin. The TXVT pin provides a center-tap to a termination network for maximum interface flexibility. Refer to the "Input Stage" section for more details.
20
/RXEN
1, 2
RXIN, /RXIN
7
/TXEN
14, 13
TXIN, /TXIN
9
TXVCTRL
11
TXVT
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SY58621L
Outputs
Pin Number 22 Pin Name LOS Pin Description Loss-of-Signal Output. TTL-compatible output with internal 4.75k pull-up resistor. Loss-ofSignal asserts to logic HIGH when the receiver input amplitudes fall below the threshold set by LOSLVL. RX Loss-of-Signal Level Set. A resistor (RLOSLVL) connected between LOSLVL and VCC sets the threshold for the data input amplitude at which the LOS output is asserted. Default is max sensitivity. LOSLVL is used to set the Loss-of-Signal (LOS) voltage. It is internally connected to a 2.8k pull-down resistor to an internal VREF voltage source. See "Typical Operating Characteristics," and "Application Implementation" sections for more details. Receiver Differential Output. Output is CML compatible. Refer to the "Truth Table" and "Output Stage" sections for more details. Unused output pair may be left open. The output is designed to drive 400mV (800mVPP) into 50 to VCC or 100 across the pair. Transmitter differential Variable Swing Output. Output is LVPECL-compatible. Please refer to the "Truth Table" section for details. Unused output pair may be left open. Each output is designed to drive 80mV (min) to 800mV (typ) into 50 to VCC-2V depending on TXVCTRL. Transmitter Output Reference Voltage. Output biases to VCC_TXQ-1.3V. Connecting VREF_CTRL to TXVCTRL sets the transmitter output swing to max swing. Transmitter Input Reference Voltage. This output biases to VCC-1.3V. It is used when AC coupling the transmitter input. For AC-coupled applications, connect TXVREF-AC to the TXVT pin and bypass with a 0.01F low ESR capacitors to VCC. See "Input Stage" section for more details. Maximum sink/source current is 1.5mA.
19
LOSLVL
17, 16
RXQ, /RXQ
5, 6 8
TXQ, /TXQ VREF_CTRL
10
TXVREF-AC
Power Pins
Pin Number 3, 24 12, 15, 18 Pin Name GND, Exposed Pad VCC Pin Description Ground. GND pins and exposed pad must be connected to the same ground plane. 3.3V 10% Positive Power Supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to each VCC pins as possible. Power pins are not connected internally and must be connected to the same power supply externally. 3.3V 10% Receive Input Power Supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to the VCC_RXIN pin as possible. Power pins are not connected internally and must be connected to the same power supply externally. 3.3V 10% Output Transmit Power Supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to the VCC_TXQ pin as possible. Power pins are not connected internally and must be connected to the same power supply externally.
21
VCC_RXIN
4
VCC_TXQ
Truth Table
LOOPBACK 0 1 RXQ RXIN TXIN TXQ TXIN RXIN
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SY58621L
Absolute Maximum Ratings(1)
Supply Voltage (VCC, VCC_TXQ, VCC_RXIN)....................... -0.5V to +4.0V Input Voltage LOSLVL ........................................... VREF -1.2V to VCC LOOPBACK ............................................. -0.5V to VCC /TXEN, /RXEN ......................................... -0.5V to VCC TXVCTRL........................... VREF_CTRL -1.2V to VCC TXIN, /TXIN.............................................. -0.5V to VCC LVPECL Output Current (IOUT) TXQ, /TXQ Continuous........................................................ 50mA Surge .............................................................. 100mA Source or Sink Current on TXVT............................................................... 100mA LOS..................................................................... 5mA RXQ, /RXQ ....................................................... 25mA RXIN, /RXIN...................................................... 10mA TXIN, /TXIN....................................................... 50mA TXVREF-AC, VREF-CTRL ............................... 2mA Lead Temperature (soldering, 20sec.) ..................... 260C Storage Temperature (Ts) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC, VCC_TXQ, VCC_RXIN) ................ +3.0V to +3.6V Ambient Temperature (TA).................. -40C to +85C Package Thermal Resistance(3) MLFTM (JA) Still-Air....................................................50C/W MLFTM (JB) Junction-to-Board...................................30C/W
DC Electrical Characteristics(4)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC VCC_TXQ VCC_RXIN ICC Parameter Power Supply Transmit Power Supply Receive Power Supply Power Supply Current No load, max. VCC Condition Min 3 3 3 Typ 3.3 3.3 3.3 100 Max 3.6 3.6 3.6 150 Units V V V mA
Receiver Input DC Electrical Characteristics
VCC_RXIN = 3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol RIN RDIFF_IN VIN VDIFF_IN VREF Parameter Input Resistance (RXIN to VREF) Input Resistance (RXIN to /RXIN) Input Voltage Swing (RXIN, /RXIN) Differential Input Voltage Swing |RXIN - /RXIN| Internal Reference Voltage See Figure 5a AC-coupled See Figure 5b AC-coupled Condition Min 45 90 10 20 VCC_RXIN -1.48 VCC_RXIN -1.32 Typ 50 100 Max 55 110 900 1800 VCC_RXIN -1.16 Units mV mV V
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
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SY58621L
Receiver Output DC Electrical Characteristics
VCC = 3.3V 10%, RL = 100 across the outputs; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOUT VDIFF_OUT ROUT RDIFF_OUT VOFFSET Parameter Output HIGH Voltage (RXQ, /RXQ) Output Voltage Swing (RXQ, /RXQ) Differential Output Voltage Swing (RXQ, /RXQ) Single-Ended Output Impedance Differential Output Impedance Differential Output Offset RL = 50 to VCC, limiting mode Condition RL = 50 to VCC See Figure 5a See Figure 5b Min VCC - 0.020 325 650 45 90 -140 Typ VCC -0.010 400 800 50 100 Max VCC 500 1000 55 110 +140 Units V mV mV mV
Transmitter Input DC Electrical Characteristics
VCC = 3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol RIN RDIFF_IN VIH VIL VIN VDIFF_IN VT_IN VTXVREF-AC VREF_CTRL VTXVCTRL Parameter Input Resistance (TXIN to TXVT) Differential Input Resistance (TXIN to /TXIN) Input HIGH Voltage (TXIN, /TXIN) Input LOW Voltage (TXIN, /TXIN) Input Voltage Swing (TXIN, /TXIN) Differential Input Voltage Swing |TXIN - /TXIN| TXIN, /TXIN to VT Output Reference Voltage Output Reference Voltage Input Voltage (TXVCTRL) VCC -1.4 VCC -1.4
VREF_CTRL
Condition
Min 45 90 1.2 0
Typ 50 100
Max 55 110 VCC VIH -0.1 VCC
Units V V V V
See Figure 5a See Figure 5b
0.1 0.2
1.28 VCC -1.3 VCC -1.3 VCC -1.3 VCC -1.3 VCC
V V V V
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SY58621L
Transmitter Output DC Electrical Characteristics
VCC_TXQ = 3.3V 10%, RL = 50 to VCC_TXQ - 2V; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOL Parameter Output HIGH Voltage (TXQ, /TXQ) Output LOW Voltage (TXQ, /TXQ) TXVCTRL = VREF_CTRL TXVCTRL = VCC_TXQ VOUT Output Voltage Swing (TXQ, /TXQ) TXVCTRL = VREF_CTRL See Figure 5a TXVCTRL = VCC_TXQ See Figure 5a VDIFF_OUT Differential Output Voltage Swing (TXQ, /TXQ) TXVCTRL = VREF_CTRL See Figure 5b TXVCTRL = VCC_TXQ See Figure 5b 1100 550 Condition Min VCC_TXQ - 1.145 VCC_TXQ - 1.945 Typ VCC_TXQ -1.020 VCC_TXQ - 1.820 VCC_TXQ - 1.100 800 80 1600 160 Max VCC_TXQ -0.895 VCC_TXQ - 1.695 Units V V V mV mV mV mV
LVTTL/CMOS INPUT DC Control Electrical Characteristics(5)
VCC = 3.3V 10%; TA = -40C to +85C, unless otherwise stated.
Symbol VIL VIH IIL IIH Parameter /TXEN, /RXEN, LOOPBACK /TXEN, /RXEN, LOOPBACK /TXEN, /RXEN, LOOPBACK /TXEN, /RXEN, LOOPBACK IIL@VIN = 0.5V IIH@VIN = VCC 2 0 50 300 Condition Min Typ Max 0.8 Units V V A A
Note: 5. /TXEN, /RXEN, and LOOPBACK have an internal pull-down 25k resistor.
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SY58621L
LOS DC Electrical Characteristics
VCC = 3.3V 10%; TA = -40C to +85C.
Symbol VLOSLVL VOH VOL VSR LOSAL Parameter LOSLVL Voltage Range Output HIGH Voltage Output LOW Voltage LOS Sensitivity Range Low LOS Assert Level RLOSLVL = 10k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps LOSDL Low LOS De-assert Level RLOSLVL = 10k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps HYSL Low LOS Hysteresis RLOSLVL = 10k, limiting mode 7 2 -1 Data Pattern, Note 6 and 7 622Mbps 3.2Gbps LOSAM Medium LOS Assert Level RLOSLVL = 5k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps LOSDM Medium LOS De-assert Level RLOSLVL = 5k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps HYSM Medium LOS Hysteresis RLOSLVL = 5k, limiting mode 7 2 -1 Data Pattern, Note 6 and 7 622Mbps 3.2Gbps LOSAH High LOS Assert Level RLOSLVL = 1k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps LOSDH High LOS De-assert Level RLOSLVL = 1k 7 2 -1 Data Pattern, Note 7 622Mbps 3.2Gbps HYSH High LOS Hysteresis RLOSLVL = 1k, limiting mode 7 2 -1 Data Pattern, Note 6 and 7 622Mbps 3.2Gbps
Notes:
Condition Source 100A; VCC 3.3V Sink 2mA
Min VREF 2.4
Typ
Max VCC 0.5
Units V V V mVPP
7
35
15 10
mV mV
20 15
mV mV
3 5.5
dB dB
20 15
mV mV
30 25
mV mV
4 5.5
dB dB
35 30
mV mV
60 55
mV mV
5 5.5
dB dB
SD_AssertVoltage 6. Hysteresis is defined as: 20Log10 SD_De - assertVoltage dB. 7. See the "Typical Operating Characteristics" section for more details on RLOSLVL and its associated LOS assert and de-assert amplitudes for a 7 7 2 -1 PRBS data pattern. See the "PRBS Discussion" section for more details on the 2 -1 PRBS data pattern.
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SY58621L
AC Electrical Characteristics(8)
VCC = VCC_TXQ = VCC_RXIN = 3.3V 10%, Receiver Load: RL = 100 across the outputs. Transmitter Load: RL = 50 to VCC_TXQ - 2V; TA = -40C to +85C, unless otherwise stated.
Receiver and Transmitter
Symbol tJITTER Parameter Deterministic Jitter (DJ) Random Jitter (RJ) Crosstalk-Induced Jitter Condition Note 9 Note 10 Note 11 0.7 Min Typ Max Note 13 5 1.2 Units psPP psRMS psRMS
Receiver
Symbol FMAX BW S21 AV(DIFF) tr, tf LOS Frequency Range tOFF tON Parameter Maximum Operating Frequency -3dB Single-Ended Gain Differential Voltage Gain Output Rise/Fall Time (20% to 80%) LOS Operating Frequency Range LOS De-assert Time LOS Assert Time Condition VRXIN 10mV (20mVPP) VRXIN 10mV (20mVPP) Linear mode Linear mode Limiting mode Note 12 0.622 Min 3.2 2.5 32 38 60 120 3.2 Typ Max Units Gbps GHz dB dB ps Gbps
0.1 0.2
0.5 0.5
s s
Transmitter
Symbol FMAX BW tr, tf
Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Deterministic jitter is measured with both K28.5 and 2 -1 PRBS data-pattern, measured at 7 23
Parameter Maximum Operating Frequency -3dB Output Rise/Fall Time (20% to 80%)
Condition VTXIN 100mV (200mVPP) VREF_CTRL TXCTRL VCC_TXQ VTXVCTRL = VREF_CTRL
Min 3.2
Typ 2 100
Max
Units Gbps GHz
160
ps
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SY58621L
Detailed Description
Receiver The receiver AC-coupled differential input distributes data to 3.2Gbps with signals as small as 10mV (20mVPP) or as large as 900mV (1.8VPP). The receiver input features an internal 50 input termination connected to an internal reference which optimizes the inputs for AC-coupled signals. Input signals are linearly amplified with 38dB of differential gain and the output signal is limited to 400mV (800mVPP). The receiver output buffer features 50 source termination resistors and a current source that provides 400mV (800mVPP) swing into 50 termination. The output buffers terminates to standard CML loads (100 across the output pair or equivalent). See the "Output Stage Receiver" section for more details. Transmitter The transmitter differential input includes Micrel's unique, patented 3-pin input termination architecture that directly interfaces to any (AC- or DC-coupled) differential signal as small as 100mV (200mVPP) without any termination resistor network in the signal path. The transmitter output buffer terminates to standard LVPECL loads (RL = 50 to VCC_TXQ-2V). The output buffer is a special variable swing LVPECL buffer controlled by TXVCTRL. The output buffer features emitter follower output that provides 80mV (160mVPP) to 800mV (1.6VPP) swing into 50 transmission lines. See the next section and Figures 1a and 1b for more details on how to control the variable output swing feature.
Figure 1b. Alternative Implementation
Transmitter PECL Variable-Swing Output Buffer * Connecting VREF_CTRL to TXVCTRL sets the transmitter output buffer to maximum swing * Setting TXVCTRL to VCC_TXQ, sets the transmitter output buffer to minimum swing * Control of the transmitter output swing buffers can be obtained by using a variable resistor connected between VREF_CTRL and VCC_TXQ with a wiper connected to TXVCTRL as shown in Figure 1b Receiver LOS The SY58621L features a chatter-free Loss-of-Signal (LOS) TTL compatible output with an internal 4.75k pull-up resistor. LOS circuitry monitors the input receiver signal and asserts a signal when the input signal falls below the threshold set by the programmable LOS level set pin (LOSLVL). When the amplitude of the receiver input signal falls below the threshold, LOS is asserted HIGH with a response time of ~0.2uS. LOS can be fed into /RXEN to maintain output stability by disabling the output during a Lossof-Signal condition. Figure 2a and 2b shows the LOS connection to /RXEN. When /RXEN is HIGH, the output signal RXQ is held LOW and /RXQ is held HIGH. Typically, 2dB of LOS hysteresis is adequate to prevent the receiver output from chattering. LOS operation is optimized for data rates 622Mbps with an input receiver amplitude of at least 10mV (20mVPP). Due to the long time constant in slower data rates below 622Mbps, the SY58621L LOS function does not guarantee chatter-free operation for low amplitude signals. LOSLVL sets the threshold of the LOS input amplitude detection. Connecting an external resistor, RLOSLVL, between VCC and LOSLVL sets the input amplitude 11
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Figure 1a. Voltage Source Implementation
September 2005
Micrel, Inc. LOS detection trip-point by setting up a voltage divider between VCC and VREF (an internal voltage source set at VCC-1.3V), since there is a 2.8k internal resistor connected between LOSLVL and VREF. The input voltage range of LOSLVL ranges from VCC to VREF. See the "Functional Block Diagram" section and Figures 2a and 2b, to see how RLOSLVL sets up a voltage divider between VCC and VREF. See the "LOS Output DC Electrical Characteristics" table and "Typical Operating Characteristics" section to see how different RLOSLVL values affect LOS sensitivity.
SY58621L * 2dB hysteresis is insured if RLOSLVL 10k * LOS is guaranteed chatter-free at f 622Mbps (311MHz) Hysteresis The SY58621L provides a minimum of 2dB of LOS hysteresis, see the Figure 3 for more details.
Figure 3. LOS Hysteresis Assert/De-assert
SD_AssertVoltage dB. SD_De - assertVoltage
Hysteresis is defined as: 20Log10
Figure 2a. Voltage Source Implementation
Loopback To support diagnostic system testing, the SY58621L features a loopback test mode, activated by setting LOOPBACK to logic HIGH. Loopback mode enables an internal loopback path from the transmitter input to the receiver output and supports the full 3.2Gbps data rate throughput. Crosstalk The SY58621L features a patent-pending isolation between the receiver and transmitter channels. The following guide lines can be used to minimize on layout induced crosstalk: 1. Ground Stripping Ground stripping is an effective method to reduce crosstalk. Ground stripping involves running a ground trace between the receiver and transmitter channels. 2. Vertical and Horizontal Traces Another way to reduce crosstalk is to route the receiver and transmitter channels on separate layers with an embedded ground or power supply layer between the layers. When routing the traces on different layers, run the receiver traces horizontal to the transmitter traces and route the transmitter traces vertical to the receiver traces.
Figure 2b. Alternative Implementation
LOS Output * Connecting the input /RXEN to the LOS output as shown in Figures 2a and 2b, maintains receiver output stability under a Loss-of-Signal condition * Sensitivity of the LOS signal can be programmed using the LOSLVL input by using a variable resistor connected to VCC with a wiper connected to LOSLVL, as shown in Figure 2b September 2005
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Micrel, Inc. PRBS Discussion
LOS Testing
SY58621L Power Supply Filtering Although the SY58621L is fully differential, it is recommended that the power supplies are filtered as shown in Figure 4.
The LOS function is tested with a 27-1 PRBS (Pseudo Random Bit Stream) data-pattern. A PRBS datapattern of 27-1 is used because it is a good approximation to an 8b10b-encoded NRZ data stream. 8b10b encodes 8 bits of data and replaces it with 10 bits of symbol. The extra bits are added to improve transition density and the BER (Bit Error Rate) of the system.
Deterministic Jitter Testing and the K28.5 Pattern
The K28.5 (11000001010011111010) and 223-1 PRBS data-patterns are used to characterize DJ because both data patterns have lower spectral frequency content which provides a best approximation to scrambled NRZ data streams.
Random Jitter Testing and the K28.7 Pattern
The K28.7 (1111100000...) data pattern is used to measure RJ since the pattern is free of DJ. In addition, because the K28.7 data-pattern can be used to compare the TN (NTH period) to the T0 (1st period), low frequency jitter components can be accumulated.
Figure 4. Power Supply Filtering Scheme Item C1, C2, C3, C23 C4, C5, C6, C22 L1, L2, L3 Description 0.1F Capacitor 0.01F Capacitor 1.2H Ferrite Bead Inductor Table 1. Bill of Materials
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Typical Operating Characteristics
VCC = VCC_TXQ = VCC_RXIN = 3.3V 10%, Receiver: RL = 100 across the outputs. Transmitter: RL = 50 to VCC_TXQ - 2V; TA = 25C, unless otherwise stated.
RLOSLVL (k)
RLOSLVL (k)
RLOSLVL (k)
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SY58621L
Single-Ended and Differential Swings
Figure 5a. Single-Ended Voltage Swing
Figure 5b. Differential Voltage Swing
Input Stage
Figure 6a. TX Simplified Differential Input Stage
Figure 6b. RX Simplified Differential Input Stage
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Output Stage
Receiver
Figure 7a. Receiver CML DC-Coupled Output
Figure 7b. Receiver CML AC-Coupled Output
Figure 7c. Receiver CML DC-Coupled Output (50 to VCC)
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SY58621L LVPECL is ideal for driving 50 and 100-controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel Termination-Thevenin Equivalent, Parallel Termination (3-Ressitor), and AC-Coupled Termination. Unused output pairs may be left floating. However, the unused half of a single-ended output must be terminated, or balanced.
Transmitter
The transmitters output is a variable swing LVPECL open emitter driver. LVPECL has very low output (open emitter) impedance, and small signal swing which result in low EMI.
Figure 8a. Parallel Thevenin-Equivalent Termination
Figure 8b. Parallel Termination - 3-Resistors
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Interface Applications
Figure 9a. LVPECL Interface (TX DC-Coupled/RX AC-Coupled)
Figure 9b. LVPECL Interface (TX AC-Coupled/RX AC-Coupled)
Figure 9c. CML Interface (TX DC-Coupled/RX AC-Coupled)
Figure 9d. CML Interface (TX AC-Coupled/RX AC-Coupled)
Figure 9e. LVDS Interface (TX DC-Coupled/RX AC-Coupled)
Related Product and Support Documentation
Part Number SY58620L HBW Solutions Function Precision 4.25Gbps CML Transceiver with Integrated Loopback New Products and Applications MLFTM Application Note Data Sheet Link www.micrel.com/product-info/products/sy58620l.shtml www.micrel.com/product-info/products/solutions.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf
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Package Information
24-Pin MLFTM (MLF-24)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated.
September 2005
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M9999-093005-A hbwhelp@micrel.com or (408) 955-1690

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